1. Field of the Invention
The present invention relates to a memory access control apparatus and method for controlling access to a memory device to be connected to a large-scale integration (LSI) device or the like.
2. Description of the Related Art
A dynamic random access memory (DRAM) is a recent example of a memory device to be connected to an LSI device or the like. Of DRAMs, a synchronous DRAM (SDRAM) passing and receiving addresses, commands, and data in synchronization with clock signals is widely used as a device that allows for high-speed access.
Methods for connecting a memory device to an LSI include the implementation of a memory device on a printed board for an LSI such that the memory device is directly connected to the LSI, and the implementation of a socket specifically designed to accommodate a module, such as a dual inline memory module (DIMM), on a printed board for an LSI such that a memory device is connected to the LSI via the socket.
In general, the former method is used for a system requiring less memory, while the latter method is used for a system requiring large amounts of memory so that memory devices can be added to the socket depending on the amount of memory required.
For the load level on a memory interface port, there is a significant difference between the case where a memory device is directly implemented on an LSI board, and the case where a memory device is connected to an LSI board via a socket specifically designed to accommodate a DIMM (hereinafter referred to as a DIMM socket). For example, for connecting a 64-bit bus SDRAM, two sets of memory devices, each having a data bus width of 32 bits, are implemented on the printed board, in the case of a system requiring less memory, whereas, in a system provided with a DIMM socket, a DIMM module with 16 sets of memory devices, each having a data bus width of 8 bits, is used.
In the former case, the load level for a data bus signal is 2, and the load level for a command/address signal is 3, whereas in the latter case, the load level for a data bus signal is 3, and the load level for a command/address signal is 17. Moreover, for the latter case, in a system provided with two sets of DIMM sockets, the load levels for a data bus signal and a command/address signal, although depending on the DIMM module used, are 5 and 33, respectively, at the maximum. In other words, for a memory device directly implemented on a printed board, there is only a small difference between a data bus signal and a command/address signal in terms of the load level, whereas for a system provided with a DIMM module, there is a large difference between a data bus signal and a command/address signal in terms of the load level.
An increase in load on a signal line causes a rise and fall of a signal waveform to become less steep. In this case, for example, in switching between Low and High levels for a short period of time, it tends to take more time for each signal to be determined. When the frequency of signal changes increases, each signal cannot be determined within a cycle expected from the control side. This is fatal to a system that passes and receives addresses, commands, and data in synchronization with clock signals.
Systems requiring large amounts of memory are becoming more common, especially in recent years. Consequently, since the load level for a command/address signal increases, it is becoming difficult to maintain synchronization between a data signal and a command/address signal while keeping a proper relationship therebetween.
A method to ensure the synchronization under heavy load conditions is to adjust the drive capability of an output buffer on the LSI side (see Japanese Patent Laid-Open No. 8-321761). According to this method, even if the load level for each signal increases, enhancing the drive capability of the output buffer can reduce a signal delay.
For load reduction, there is a method using a registered DIMM (see Japanese Patent Laid-Open No. 2003-345652). In this method, a command/address signal is temporarily stored in a register on the DIMM module side, and then transmitted to a port for a command/address signal in each device in the DIMM module. Load reduction can be achieved by temporarily storing a command/address signal in the register, since split signals are received at a single port.
However, in the above-described method to ensure the synchronization, it is extremely difficult, only by adjusting the drive capability of the output buffer, to perform control covering all combinations of various numbers of DIMM modules and various numbers of memory devices in each DIMM module. Therefore, in a system requiring large amounts of memory, it is extremely difficult by this method to eliminate the negative effects of a delay and less steep curve of signals.
As for the above-described method for load reduction, there is a problem in that the implementation of the register on the DIMM module results in increased costs of the module and system.